As we told you earlier, the 3D-stacked chiplets based on the Zen 3 architecture will go into production this year. The latter will allow you to add an additional 64MB of 7nm SRAM cache (called 3D V-Cache) stacked vertically on top of the Core Complex Die (CCD) to triple the amount of L3 cache for the CPU cores. This technique can provide up to 192MB of L3 cache for Ryzen processors, a substantial improvement over the current 64MB limit.
The technology currently consists of a single stacked L3 cache layer, but will be supported in the future even stacking multiple dies. It also requires no specific software optimization and should be transparent in terms of latency and thermal requirements (no significant overhead for either). The 3D stacking of the 3D chips is based on TSMC's SoIC technology. As shown in the video, AMD flipped the die and reduced the standard compute die by 95% leaving only 20 micrometers of active silicon for computation purposes. Finally, a standard L3 chip was placed on top to complete the stack.
As we already know, TSMC's SoIC is a stacking technology that does not use microbumps or soldering to connect the two dies. Instead, these are milled onto a surface so perfectly flat that the TSV channels can mate without any kind of adhesive material, reducing the distance between the cache and the core by a thousandfold. This reduces heat and power consumption while bandwidth is increased.
The video contains much more detail and explains the chip interconnect technology, which is quite interesting and informative, as well as providing some more detail about AMD's new stacking technique.
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